Semiconductor device

ABSTRACT

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2021-086663, filed on May 24,2021, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The embodiments discussed herein relate to a semiconductor device.

2. Background of the Related Art

Semiconductor devices include semiconductor chips used as a powerconverter. The semiconductor chips are insulated gate bipolartransistors (IGBTs), power metal oxide semiconductor field effecttransistors (MOSFETs), or the like. Such a semiconductor device includesin a case at least semiconductor chips, external connection terminals,and an insulated circuit board over which the semiconductor chips andexternal connection terminals are arranged. Each part is sealed with asealing member in the case. The insulated circuit board includes aninsulating plate, circuit patterns formed over the front surface of theinsulating plate, and a metal plate formed on the back surface of theinsulating plate. The semiconductor chips and the external connectionterminals are bonded to the front surfaces of the circuit patterns withsolder. Furthermore, the back surface of the metal plate of theinsulated circuit board is exposed on the back surface of thesemiconductor device (see, for example, Japanese Laid-open PatentPublication No. 2021-019064).

With the above semiconductor device a resistance element is arrangedover a circuit pattern and a circuit including the resistance element isformed. By doing so, a potential between electrodes is measured. Theresistance element is a shunt resistor or the like. A shunt resistorincludes a resin layer and a resistance film and electrodes formedthereover. Furthermore, with the shunt resistor the resin layer isformed over a metal block in order to dissipate heat.

However, even if the shunt resistor simply includes the metal block, theshunt resistor which generates heat is not sufficiently cooled. If heatgenerated by the shunt resistor is transferred to surroundings, then theheat dissipation property of the whole semiconductor devicedeteriorates. This leads to deterioration in the reliability of thesemiconductor device.

SUMMARY OF THE INVENTION

According to an aspect, there is provided a semiconductor device,including: a resistance element including a metal block, a resin layerdisposed on the metal block, and a resistance film disposed on the resinlayer; and an insulated circuit board including an insulating plate, anda circuit pattern having a front surface, the circuit pattern beingdisposed on the insulating plate and having a bonding area on the frontsurface of the circuit pattern to which a back surface of the metalblock of the resistance element is bonded, an area of the circuitpattern being larger in a plan view of the semiconductor device than anarea of the resistance element, wherein the metal block has a thicknessgreater than a thickness of the circuit pattern in a directionorthogonal to the back surface of the metal block.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device according to a firstembodiment;

FIG. 2 is a sectional view of the semiconductor device according to thefirst embodiment;

FIG. 3 is a fragmentary plan view of a semiconductor device according toa second embodiment;

FIG. 4 is a fragmentary sectional view of the semiconductor deviceaccording to the second embodiment;

FIG. 5 is a fragmentary plan view of modification 2-1 of thesemiconductor device according to the second embodiment;

FIG. 6 is a fragmentary sectional view of modification 2-1 of thesemiconductor device according to the second embodiment;

FIG. 7 is a fragmentary plan view of modification 2-2 of thesemiconductor device according to the second embodiment;

FIG. 8 is a fragmentary plan view of modification 2-3 of thesemiconductor device according to the second embodiment;

FIG. 9 is a fragmentary sectional view of modification 2-3 of thesemiconductor device according to the second embodiment;

FIG. 10 is a fragmentary plan view of modification 2-4 of thesemiconductor device according to the second embodiment;

FIG. 11 is a fragmentary sectional view of modification 2-4 of thesemiconductor device according to the second embodiment;

FIG. 12 is a fragmentary plan view of modification 2-5 of thesemiconductor device according to the second embodiment;

FIG. 13 is a fragmentary sectional view of modification 2-5 of thesemiconductor device according to the second embodiment;

FIG. 14 is a fragmentary plan view of a semiconductor device accordingto a third embodiment;

FIG. 15 is a fragmentary sectional view of the semiconductor deviceaccording to the third embodiment;

FIG. 16 is a fragmentary plan view of a semiconductor device accordingto a fourth embodiment;

FIG. 17 is a fragmentary sectional view of the semiconductor deviceaccording to the fourth embodiment;

FIG. 18 is a fragmentary sectional view of a semiconductor deviceaccording to a fifth embodiment;

FIG. 19 is a fragmentary plan view of a semiconductor device accordingto a sixth embodiment; and

FIG. 20 is a fragmentary sectional view of the semiconductor deviceaccording to the sixth embodiment.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will now be described by reference to the accompanyingdrawings. In the following description a “front surface” and an “uppersurface” indicate an X-Y plane of a semiconductor device 1 of FIG. 1which faces the upper side (+Z direction). Similarly, an “upside”indicates the upward direction (+Z direction) of the semiconductordevice 1 of FIG. 1. A “back surface” and a “lower surface” indicate theX-Y plane of the semiconductor device 1 of FIG. 1 which faces the lowerside (−Z direction). Similarly, a “downside” indicates the downwarddirection (−Z direction) of the semiconductor device 1 of FIG. 1. Theseterms mean the same directions at need in the other drawings. The “frontsurface,” the “upper surface,” the “upside,” the “back surface,” the“lower surface,” the “downside,” and a “side” are simply used asexpedient representation for specifying relative positionalrelationships and do not limit the technical idea of the presentdisclosure. For example, the “upside” and the “downside” do not alwaysmean the vertical direction relative to the ground. That is to say, thedirections indicated by the “upside” and the “downside” are not limitedto the gravity direction. Furthermore, in the following description a“main component” indicates a component contained at a rate of 80 volumepercent (vol %) or more.

First Embodiment

A semiconductor device according to a first embodiment will be describedby the use of FIG. 1 and FIG. 2. FIG. 1 is a plan view of asemiconductor device according to the first embodiment. FIG. 2 is asectional view of the semiconductor device according to the firstembodiment. FIG. 2 is a sectional view taken along the dot-dash line X-Xof FIG. 1.

A semiconductor device 1 includes an insulated circuit board 2, asemiconductor chip 6 and a resistance element 7 mounted over theinsulated circuit board 2, and main current terminals 8 d and 8 e andcurrent sense terminals 8 f and 8 g mounted over the insulated circuitboard 2. With the semiconductor device 1, these are housed in a case 20and the inside of the case 20 is sealed with a sealing member 21.

The insulated circuit board 2 is rectangular in plan view. The insulatedcircuit board 2 includes an insulating plate 3, a plurality of circuitpatterns 4 a through 4 h formed over the front surface of the insulatingplate 3, and a metal plate 5 formed on the back surface of theinsulating plate 3. The insulating plate 3 and the metal plate 5 arerectangular in plan view. Furthermore, corner portions of the insulatingplate 3 and the metal plate 5 may be R-chamfered or C-chamfered. Themetal plate 5 is smaller in size than the insulating plate 3 in planview and is formed inside the insulating plate 3. The insulating plate 3has an insulating property and is made of a ceramic having high thermalconductivity. Such a ceramic is made of a material which contains as amain component aluminum oxide, aluminum nitride, silicon nitride, or thelike. In addition, the thickness of the insulating plate 3 is greaterthan or equal to 0.5 mm and smaller than or equal to 2.0 mm.

The circuit patterns 4 a through 4 h are made of metal having goodelectrical conductivity. For example, such metal is silver, copper,nickel, or an alloy containing at least one of them. In this embodimentthe circuit patterns 4 a through 4 h are made of metal which contains asa main component copper or a copper alloy. Furthermore, the thickness T2of the circuit patterns 4 a through 4 h is greater than or equal to 0.2mm and smaller than or equal to 1.5 mm. In this embodiment the thicknessT2 of the circuit patterns 4 a through 4 h is 0.3 mm. In order toimprove corrosion resistance, plating treatment may be performed on thesurfaces of the circuit patterns 4 a through 4 h. At this time nickel, anickel-phosphorus alloy, a nickel-boron alloy or the like is used as aplating material. The circuit patterns 4 a through 4 h are formed overthe insulating plate 3 in the following way. A metal layer is formedover the front surface of the insulating plate 3 and etching, cutting,laser processing, or the like is performed on the metal layer. By doingso, the circuit patterns 4 a through 4 h are obtained. Alternatively,the circuit patterns 4 a through 4 h cut in advance out of a metal layermay be pressure-bonded to the front surface of the insulating plate 3.In addition, corner portions of each of the circuit patterns 4 a through4 h are R-chamfered. The circuit patterns 4 a through 4 h illustrated inFIG. 1 and FIG. 2 are taken as an example. The quantity, shape, size,and the like of the circuit patterns 4 a through 4 h may be properlyselected at need. When no distinction is made between the circuitpatterns 4 a through 4 h, then the circuit patterns 4 a through 4 h maybe referred to as the circuit patterns 4.

The metal plate 5 is made of metal, such as aluminum, iron, silver,copper, or an alloy containing at least one of them, having high thermalconductivity. Furthermore, corner portions of the metal plate 5 may beR-chamfered. The thickness of the metal plate 5 is greater than or equalto 0.2 mm and smaller than or equal to 0.4 mm. In order to improvecorrosion resistance, plating treatment may be performed on the surfaceof the metal plate 5. At this time nickel, a nickel-phosphorus alloy, anickel-boron alloy, or the like is used as a plating material.

A direct copper bonding (DCB) substrate, an active metal brazed (AMB)substrate, or the like may be used as the above insulated circuit board2. Furthermore, a thermally conductive member is located on the backsurface of the metal plate 5 of the insulated circuit board 2 of thesemiconductor device 1. A radiation unit (not illustrated) is fixed onthe back surface of the metal plate 5 with the thermally conductivemember therebetween. This improves the heat dissipation property of thesemiconductor device 1 further. The thermally conductive member is athermal interface material (TIM). A TIM is a generic name for variousthermally conductive materials such as a grease, an elastomer sheet,room temperature vulcanization (RTV) rubber, gel, or a phase changematerial.

The semiconductor chip 6 is a switching element or a diode element madeof silicon or silicon carbide. The semiconductor chip 6 has the shape ofa flat plate and is rectangular in plan view. If the semiconductor chip6 is a switching element, then the semiconductor chip 6 is an IGBT, apower MOSFET, or the like. If the semiconductor chip 6 is an IGBT, thenthe semiconductor chip 6 has a collector electrode, which is rectangularin plan view, as a main electrode on the back surface and has a gateelectrode, which is rectangular in plan view, on a central portion ofone end portion of the front surface and an emitter electrode as a mainelectrode on an area except the gate electrode of the front surface. Ifthe semiconductor chip 6 is a power MOSFET, then the semiconductor chip6 has a drain electrode, which is rectangular in plan view, as a mainelectrode on the back surface and has a gate electrode, which isrectangular in plan view, on a central portion of one end portion of thefront surface and a source electrode as a main electrode on an areaexcept the gate electrode of the front surface.

Furthermore, if the semiconductor chip 6 is a diode element, then thesemiconductor chip 6 is a free wheeling diode (FWD) such as a Schottkybarrier diode (SBD) or a P-intrinsic-N (PiN) diode. In this case, thesemiconductor chip 6 has a cathode electrode, which is rectangular inplan view, as a main electrode on the back surface and has an anodeelectrode, which is rectangular in plan view, as a main electrode on thefront surface.

The resistance element 7 is a shunt resistor. The resistance element 7is rectangular in plan view and the length of its one side is greaterthan or equal to 9.0 mm and smaller than or equal to 12 mm. Furthermore,the height (length from the back surface to the front surface in sideview) of the resistance element 7 is greater than or equal to 0.5 mm andsmaller than or equal to 0.7 mm. The resistance element 7 is bonded to abonding area 4 a 1 on the front surface of the circuit pattern 4 a. Theouter periphery of the bonding area 4 a 1 may correspond to the outerperiphery of the back surface of the resistance element 7 (metal block 7a described later). That is to say, the bonding area 4 a 1 isrectangular in plan view and may be equal in area to the resistanceelement 7. There is need for the front surface of the circuit pattern 4a to be larger in plan view than the bonding area 4 a 1. The externalshape of the circuit pattern 4 a may be a rectangle in plan view whichis a size larger than the bonding area 4 a 1. The resistance element 7includes the metal block 7 a, a resin layer 7 b, a resistance film 7 c,main current electrodes 7 d 1 and 7 d 2, and measurement electrodes 7 d3 and 7 d 4.

The metal block 7 a has the shape of a cube (shape of a block). Thefront surface and back surface of the metal block 7 a are equal inexternal shape and area. The metal block 7 a is rectangular in plan viewand the length of its one side is greater than or equal to 9.0 mm andsmaller than or equal to 12 mm. Furthermore, the thickness T1 of themetal block 7 a is greater than or equal to 0.3 mm and smaller than orequal to 1.0 mm. In this embodiment the thickness T1 of the metal block7 a is 0.5 mm. That is to say, it is preferable that the thickness T1 ofthe metal block 7 a be greater than or equal to 1.2 times the thicknessT2 of the circuit pattern 4 a and smaller than or equal to 5.0 times thethickness T2 of the circuit pattern 4 a. It is more preferable that thethickness T1 of the metal block 7 a be greater than or equal to 1.5times the thickness T2 of the circuit pattern 4 a and smaller than orequal to 3.0 times the thickness T2 of the circuit pattern 4 a.

Furthermore, as stated above, the back surface of the metal block 7 a(resistance element 7) is bonded to the bonding area 4 a 1 of thecircuit pattern 4 a. At this time an outer peripheral portion of thecircuit pattern 4 a may extend outside an outer peripheral portion ofthe bonding area 4 a 1 by the thickness (0.5 mm) of the metal block 7 aor more. In addition, it is preferable that the outer peripheral portionof the circuit pattern 4 a extend outside the outer peripheral portionof the bonding area 4 a 1 by 2 times (1.0 mm) the thickness of the metalblock 7 a or more.

The metal block 7 a is made of metal, such as silver, copper, nickel, oran alloy containing at least one of them, having good electricalconductivity. In this case, the metal block 7 a is made of metal whichcontains as a main component copper or a copper alloy. In order toimprove corrosion resistance, plating treatment may be performed on thesurface of the metal block 7 a. At this time nickel, a nickel-phosphorusalloy, a nickel-boron alloy or the like is used as a plating material.

The resin layer 7 b is formed over the whole of the front surface of themetal block 7 a. The resin layer 7 b is made of resin, such as epoxyresin, phenolic resin, silicone resin, or polyimide resin, having aninsulating property and a heat resistance property. The thickness of theresin layer 7 b is greater than or equal to 0.1 mm and smaller than orequal to 0.15 mm.

The resistance film 7 c is formed in plan view over a central portion ofthe front surface of the resin layer 7 b. One side of the resistancefilm 7 c is situated on one edge side of the resin layer 7 b. A recessis formed on another side opposite the one side of the resistance film 7c. That is to say, projections are formed on both ends of the other sideof the resistance film 7 c. Furthermore, the resistance film 7 c is ametal thin film which contains as a main component silver, copper,nickel, gold, an alloy containing at least one of them, or the like. Theresistance film 7 c, which is such a metal thin film, is formed over theresin layer 7 b by evaporation, sputtering, plasma chemical vapordeposition (CVD), or the like. The thickness of the resistance film 7 cis greater than or equal to 0.05 mm and smaller than or equal to 0.07mm.

The main current electrodes 7 d 1 and 7 d 2 and the measurementelectrodes 7 d 3 and 7 d 4 are made of metal having good electricalconductivity. Such a metal contains as a main component silver, copper,nickel, an alloy containing at least one of them, or the like. In thiscase, the main current electrodes 7 d 1 and 7 d 2 and the measurementelectrodes 7 d 3 and 7 d 4 are made of metal which contains as a maincomponent copper or a copper alloy. In order to improve corrosionresistance, plating treatment may be performed on the surfaces of themain current electrodes 7 d 1 and 7 d 2 and the measurement electrodes 7d 3 and 7 d 4. At this time nickel, a nickel-phosphorus alloy, anickel-boron alloy or the like is used as a plating material.

Furthermore, each of the main current electrodes 7 d 1 and 7 d 2 isformed so as to be a rectangular pattern. Each of the main currentelectrodes 7 d 1 and 7 d 2 is formed on a side portion of the resistancefilm 7 c over the front surface of the resin layer 7 b. At this time themain current electrodes 7 d 1 and 7 d 2 are in contact with the sideportions of the resistance film 7 c. That is to say, the main currentelectrodes 7 d 1 and 7 d 2 are situated over an outer peripheral portionof the resin layer 7 b.

Each of the measurement electrodes 7 d 3 and 7 d 4 is formed so as to bea rectangular pattern. The measurement electrodes 7 d 3 and 7 d 4 areparallel to the main current electrodes 7 d 1 and 7 d 2 respectively andare formed on the opposite sides of the main current electrodes 7 d 1and 7 d 2, respectively, with respect to the resistance film 7 c overthe front surface of the resin layer 7 b. At this time the measurementelectrodes 7 d 3 and 7 d 4 are in contact with the two projections,respectively, of the resistance film 7 c. That is to say, themeasurement electrodes 7 d 3 and 7 d 4 are also situated over the outerperipheral portion of the resin layer 7 b.

Furthermore, the back surfaces of the semiconductor chip 6 and theresistance element 7 are bonded to the circuit patterns 4 b and 4 a,respectively, with a bonding member 7 e (FIG. 2). A sintered metal bodyor solder is used as the bonding member 7 e. Metal microparticle powderused for the sintered metal body contains as a main component silver,copper, an alloy containing at least one of them, or the like. Inaddition, for example, Pb-free solder is used as the solder. The Pb-freesolder contains as a main component at least one of a tin-silver-copperalloy, a tin-zinc-bismuth alloy, a tin-copper alloy, and atin-silver-indium-bismuth alloy, and the like. Moreover, the solder maycontain an additive such as nickel, germanium, cobalt, or silicon. Thesolder containing an additive improves wettability, a gloss, and bondingstrength and reliability is improved. In this embodiment a case wherethe bonding member 7 e is solder is taken as an example. The thicknessof the bonding member 7 e used for bonding the resistance element 7 andthe circuit pattern 4 a together is greater than or equal to 0.05 mm andsmaller than or equal to 0.20 mm. In this embodiment the thickness ofthe bonding member 7 e is 0.10 mm.

The main current terminals 8 d and 8 e and the current sense terminals 8f and 8 g are made of metal having good electrical conductivity. Such ametal contains as a main component silver, copper, nickel, an alloycontaining at least one of them, or the like. In this case, the maincurrent terminals 8 d and 8 e and the current sense terminals 8 f and 8g are made of metal which contains as a main component copper or acopper alloy. In order to improve corrosion resistance, platingtreatment may be performed on the surfaces of the main current terminals8 d and 8 e and the current sense terminals 8 f and 8 g. At this timenickel, a nickel-phosphorus alloy, a nickel-boron alloy or the like isused as a plating material. Furthermore, the main current terminals 8 dand 8 e and the current sense terminals 8 f and 8 g may have the shapeof a pole. The main current terminals 8 d and 8 e and the current senseterminals 8 f and 8 g are bonded to the circuit patterns 4 d, 4 e, 4 f,and 4 g, respectively, with the above bonding member. In addition, themain current terminals 8 d and 8 e and the current sense terminals 8 fand 8 g may be bonded directly to the circuit patterns 4 d, 4 e, 4 f,and 4 g, respectively, by the use of ultrasonic waves or laser beams.

Bonding wires 9 a and 9 b connect the main current electrodes 7 d 1 and7 d 2 of the resistance element 7 and the circuit patterns 4 d and 4 c,respectively, electrically and mechanically. Bonding wires 9 e and 9 fconnect the measurement electrodes 7 d 3 and 7 d 4 of the resistanceelement and the circuit patterns 4 f and 4 g, respectively, electricallyand mechanically. Furthermore, a bonding wire 9 c connects the circuitpatterns 4 e and 4 b electrically and mechanically. A bonding wire 9 dconnects the main electrode on the front surface of the semiconductorchip 6 and the circuit pattern 4 c electrically and mechanically. Abonding wire 9 g connects the control electrode of the semiconductorchip 6 and the circuit pattern 4 h electrically and mechanically. Thebonding wires 9 a through 9 g are made of a material having goodelectrical conductivity. Such a material contains as a main componentgold, silver, copper, aluminum, an alloy containing at least one ofthem, or the like. In addition, for example, the diameter of the bondingwires 9 e through 9 g is greater than or equal to 110 μm and smallerthan or equal to 200 μm. For example, the diameter of the bonding wires9 a through 9 d is greater than or equal to 350 μm and smaller than orequal to 500 μm.

The case 20 houses the circuit patterns 4 on the front surface of theinsulated circuit board 2, the semiconductor chip 6, the resistanceelement 7, one end portions of the main current terminals 8 d and 8 eand the current sense terminals 8 f and 8 g, and the bonding wires 9 athrough 9 g. The other end portions of the main current terminals 8 dand 8 e and the current sense terminals 8 f and 8 g may extend upward(in the +Z direction) from the front surface of the case 20. The case 20is made of resin. Such resin contains as a main component athermoplastic resin such as polyphenylene sulfide resin, polybutyleneterephthalate resin, polybutylene succinate resin, polyamide resin, oracrylonitrile butadiene styrene resin.

The sealing member 21 may seal the inside of the case 20. That is tosay, the sealing member 21 seals the circuit patterns 4 on the frontsurface of the insulated circuit board 2, the semiconductor chip 6, theresistance element 7, the one end portions of the main current terminals8 d and 8 e and the current sense terminals 8 f and 8 g, and the bondingwires 9 a through 9 g. For example, the sealing member contains athermosetting resin and a filling material contained in a thermosettingresin. A thermosetting resin is epoxy resin, phenolic resin, maleimideresin, or the like. An example of the sealing member 21 is epoxy resincontaining a filling material. An inorganic material, such as siliconoxide, aluminum oxide, boron nitride, or aluminum nitride, is used asthe filling material. Silicone gel may be used as the sealing member 21in place of the above materials.

With the semiconductor device 1 the main electrode on the back surfaceof the semiconductor chip 6 is electrically connected via the circuitpattern 4 e, the bonding wire 9 c, and the circuit pattern 4 b to themain current terminal 8 e which is a P terminal. Furthermore, the mainelectrode on the front surface of the semiconductor chip is electricallyconnected via the bonding wire 9 d, the circuit pattern 4 c, the bondingwire 9 b, the resistance element 7, the bonding wire 9 a, and thecircuit pattern 4 d to the main current terminal 8 d which is an Nterminal. The control electrode of the semiconductor chip 6 iselectrically connected via the bonding wire 9 g and the circuit pattern4 h to a control terminal 8 h. Accordingly, when a control signal isinputted to the control terminal 8 h of the semiconductor device 1 atdetermined timing, a current is outputted from the main electrode on thefront surface of the semiconductor chip 6 according to the controlsignal. The current outputted from the semiconductor chip 6 is inputtedto the main current electrode 7 d 2 of the resistance element 7, flowsthrough the resistance film 7 c, and is outputted from the main currentelectrode 7 d 1. At this time the current flowing through the resistancefilm 7 c is outputted via the measurement electrodes 7 d 4 and 7 d 3,the bonding wires 9 f and 9 e, and the circuit patterns 4 g and 4 f fromthe current sense terminals 8 g and 8 f. A potential is measured on thebasis of this current.

When the current outputted from the semiconductor chip 6 flows throughthe resistance film 7 c of the resistance element 7, the resistance film7 c generates heat. In this case, the metal block 7 a included in theresistance element 7 is sufficiently thicker than the circuit patterns4. Accordingly, the resistance element 7 properly conducts the heatgenerated by the resistance film 7 c from the metal block 7 a to thecircuit pattern 4 a and dissipates the heat via the circuit pattern 4 a,the insulating plate 3, and the metal plate 5 to the outside.

The above semiconductor device 1 has the resistance element 7 includingthe metal block 7 a, the resin layer 7 b formed over the metal block 7a, and the resistance film 7 c formed over the resin layer 7 b and theinsulated circuit board 2 including the insulating plate 3 and thecircuit pattern 4 a formed over the insulating plate 3, having on thefront surface the bonding area 4 a 1 to which the back surface of themetal block 7 a of the resistance element 7 is bonded, and having arealarger in plan view than that of the front surface of the resistanceelement 7. In this case, the metal block 7 a is thicker than the circuitpattern 4 a. As a result, the metal block 7 a properly conducts heatgenerated by the resistance film 7 c of the resistance element 7 to thecircuit pattern 4 a. This improves the heat dissipation property of theresistance element 7 and suppresses deterioration in the heatdissipation property of the insulated circuit board 2. Accordingly,deterioration in the reliability of the semiconductor device 1 is alsosuppressed.

Second Embodiment

A semiconductor device according to a second embodiment will bedescribed by the use of FIG. 3 and FIG. 4. FIG. 3 is a fragmentary planview of a semiconductor device according to a second embodiment. FIG. 4is a fragmentary sectional view of the semiconductor device according tothe second embodiment. FIG. 3 is an enlarged plan view of the vicinitiesof a resistance element 7 of a semiconductor device 1 a. FIG. 4 is anenlarged sectional view of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 3. In the second embodiment achange made in the semiconductor device 1 according to the firstembodiment will mainly be described. Furthermore, components of thesemiconductor device 1 a which are the same as those included in thesemiconductor device 1 according to the first embodiment are marked withthe same numerals and descriptions of them will be omitted orsimplified.

With the semiconductor device 1 a according to the second embodiment aconcave portion (concavity) is formed in at least one of areascorresponding to four corners of the bonding area 4 a 1 of the circuitpattern 4 a over which the resistance element 7 of the semiconductordevice 1 according to the first embodiment is arranged. The areascorresponding to the four corners of the bonding area 4 a 1 mean areasoutside and near corner portions of the bonding area 4 a 1. FIGS. 3 and4 illustrate as a desirable case a case where concave portions 10 a 1through 10 a 4 are formed in areas corresponding to all of the fourcorners of the bonding area 4 a 1. The concave portions 10 a 1 through10 a 4 may be circular, elliptic, or rectangular in plan view.Furthermore, the diameter of the concave portions 10 a 1 through 10 a 4is set so that the strength of a circuit pattern 4 a will not fall. Thediameter of the concave portions 10 a 1 through 10 a 4 is greater thanor equal to 50 percent of a gap between an outer peripheral portion ofthe circuit pattern 4 a and an outer peripheral portion of the bondingarea 4 a 1 (resistance element 7) and smaller than or equal to 85percent of the gap. The depth of the concave portions 10 a 1 through 10a 4 is set so that they will not pierce the circuit pattern 4 a. Thedepth of the concave portions 10 a 1 through 10 a 4 is greater than orequal to 50 percent of the thickness T2 of the circuit pattern 4 a andsmaller than or equal to 70 percent of the thickness T2 of the circuitpattern 4 a. In addition, the concave portions 10 a 1 through 10 a 4 areformed in the circuit pattern 4 a by etching, cutting, laser processing,or the like.

With the semiconductor device 1 according to the first embodiment, asstated above, the metal block 7 a is made thicker than the circuitpattern 4 a. By doing so, the heat dissipation property of theresistance element 7 is improved. If the heat dissipation property ofthe resistance element 7 is improved, then the amount of heat conductedto the circuit pattern 4 a increases. If temperature cycling isperformed on the semiconductor device 1, then the temperature of thecircuit pattern 4 a changes according to a rise or fall in temperature.In particular, heat is conducted from the metal block 7 a to the circuitpattern 4 a. As a result, a temperature differential of the circuitpattern 4 a becomes greater and the circuit pattern 4 a expands andcontracts more. Because there is a difference in thermal expansioncoefficient between the circuit pattern 4 a and the insulating plate 3,there is a case where the insulating plate 3 does not accommodateexpansion and contraction of the circuit pattern 4 a. Accordingly, greatstress is applied to the insulating plate 3 under a corner portion ofthe circuit pattern 4 a and a crack may appear. At this time a cracktends to appear from each corner portion of the back surface of thecircuit pattern 4 a to the inside of the insulating plate 3. Inparticular, if the gap between the outer peripheral portion of thecircuit pattern 4 a and the outer peripheral portion of the bonding area4 a 1 is small, then damage to the insulating plate 3 occurssignificantly. As the gap between the outer peripheral portion of thecircuit pattern 4 a and the outer peripheral portion of the bonding area4 a 1 becomes larger, stress applied from each corner portion of theback surface of the circuit pattern 4 a to the insulating plate 3 isrelaxed.

Accordingly, the concave portions 10 a 1 through 10 a 4 are formed inplan view in the areas corresponding to the four corners of the bondingarea 4 a 1 of the semiconductor device 1 a according to the secondembodiment. There is a gap between an outer peripheral portion of thecircuit pattern 4 a and an outer peripheral portion of the bonding area4 a 1. For example, the concave portions 10 a 1 through 10 a 4 areformed in this gap outside the four corners of the bonding area 4 a 1.Furthermore, as illustrated in FIG. 3, the concave portions 10 a 1through 10 a 4 may be formed in plan view outside the four corners ofthe bonding area 4 a 1 and inside the four corners of the circuitpattern 4 a.

That is to say, the volume of the areas corresponding to the fourcorners of the bonding area 4 a 1 is small compared with that of thefour corners of the circuit pattern 4 a in the first embodiment.Accordingly, even if the circuit pattern 4 a expands and contracts byperforming temperature cycling on the semiconductor device 1 a, thecircuit pattern 4 a is hardly pulled from the insulating plate 3 becauseof the small volume of the four corners of the circuit pattern 4 a.Furthermore, the concave portions 10 a 1 through 10 a 4 are formed inthe four corners of the circuit pattern 4 a in which stress speciallytends to concentrate. As a result, stress applied to the insulatingplate 3 under the corner portions of the circuit pattern 4 a is relaxedand the appearance of a crack is suppressed.

With the above semiconductor device 1 a, heat generated by a resistanceelement 7 is dissipated and deterioration in the heat dissipationproperty of an insulated circuit board 2 is suppressed. Furthermore,stress applied to the insulating plate 3 under the corner portions ofthe circuit pattern 4 a is relaxed and the appearance of a crack issuppressed. As a result, the occurrence of damage to the insulatedcircuit board 2 is prevented and deterioration in the heat dissipationproperty of the insulated circuit board 2 is also suppressed.Accordingly, deterioration in the reliability of the semiconductordevice 1 a is also suppressed.

Various forms of concave portions formed in the circuit pattern 4 a willnow be described as modifications.

(Modification 2-1)

A semiconductor device 1 a according to modification 2-1 will bedescribed by the use of FIG. 5 and FIG. 6. FIG. 5 is a fragmentary planview of modification 2-1 of the semiconductor device according to thesecond embodiment. FIG. 6 is a fragmentary sectional view ofmodification 2-1 of the semiconductor device according to the secondembodiment. FIG. 5 is an enlarged plan view of the vicinities of aresistance element 7 of a semiconductor device 1 a. FIG. 6 is anenlarged sectional view of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 5. In modification 2-1 achange made in the semiconductor device 1 a according to the secondembodiment will mainly be described. Furthermore, components of thesemiconductor device 1 a according to modification 2-1 which are thesame as those included in the semiconductor device 1 according to thefirst embodiment are marked with the same numerals and descriptions ofthem will be omitted or simplified.

With the semiconductor device 1 a according to modification 2-1 concaveportions 10 a 1 through 10 a 4 are formed so as to overlap four corners,respectively, of a bonding area 4 a 1 in plan view. For example, aconcave portion is formed in a circuit pattern 4 a so as to overlap atleast one of the four corners of the bonding area 4 a 1 in plan view.FIGS. 5 and 6 illustrate as a desirable case a case where the concaveportions 10 a 1 through 10 a 4 are formed under four corners,respectively, of the resistance element 7. As a result, stress appliedby an outer peripheral portion of the resistance element 7 is relaxed.Furthermore, in this case, the concave portions 10 a 1 through 10 a 4are also filled with a bonding member 7 e which is solder.

With the semiconductor device 1 a according to modification 2-1, heatgenerated by the resistance element 7 is dissipated and deterioration inthe heat dissipation property of an insulated circuit board 2 issuppressed. Furthermore, stress applied to an insulating plate 3 underthe corner portions of the circuit pattern 4 a is relaxed and theappearance of a crack is suppressed. As a result, the occurrence ofdamage to the insulated circuit board 2 is prevented. In addition, theconcave portions 10 a 1 through 10 a 4 are also filled with the bondingmember 7 e and wet-spreading of the bonding member 7 e is prevented.This improves bonding strength between the resistance element 7 and thecircuit pattern 4 a. Accordingly, deterioration in the reliability ofthe semiconductor device 1 a is also suppressed.

(Modification 2-2)

A semiconductor device 1 a according to modification 2-2 will bedescribed by the use of FIG. 7. FIG. 7 is a fragmentary plan view ofmodification 2-2 of the semiconductor device according to the secondembodiment. FIG. 7 is an enlarged plan view of the vicinities of aresistance element 7 of a semiconductor device 1 a. Furthermore, FIG. 4may be referred to for a sectional view of modification 2-2 taken alongthe dot-dash line X-X of FIG. 7. In modification 2-2 a change made inthe semiconductor device 1 a according to the second embodiment willalso mainly be described. In addition, components of the semiconductordevice 1 a according to modification 2-2 which are the same as thoseincluded in the semiconductor device 1 a according to the secondembodiment are marked with the same numerals and descriptions of themwill be omitted or simplified.

With the semiconductor device 1 a according to modification 2-2 aplurality of concave portions 10 a are formed between the concaveportions 10 a 1 through 10 a 4 along each side of the circuit pattern 4a illustrated in FIG. 3. As described in FIG. 3 and FIG. 4, greaterstress is applied to the insulating plate 3 under a corner portion ofthe circuit pattern 4 a due to a change in temperature. Furthermore, atthis time stress may also be applied to the insulating plate 3 under anouter peripheral portion of the resistance element 7.

Accordingly, with the semiconductor device 1 a according to modification2-2 concave portions 10 a are formed along each side of a resistanceelement 7 in addition to concave portions 10 a 1 through 10 a 4 in thefour corners of a circuit pattern 4 a. As a result, stress applied to aninsulating plate 3 is relaxed more reliably compared with thesemiconductor device 1 a illustrated in FIG. 3 and FIG. 4 and theappearance of a crack is suppressed more reliably.

In modification 2-2, as with modification 2-1, the concave portions 10 a1 through 10 a 4 and the concave portions 10 a may be formed in thecircuit pattern 4 a so as to overlap the outer peripheral portion of theresistance element 7 (bonding area 4 a 1) in plan view. By doing so,stress applied to the insulating plate 3 under the outer peripheralportion of the resistance element 7 is relaxed compared with the case ofmodification 2-1.

(Modification 2-3)

A semiconductor device 1 a according to modification 2-3 will bedescribed by the use of FIG. 8 and FIG. 9. FIG. 8 is a fragmentary planview of modification 2-3 of the semiconductor device according to thesecond embodiment. FIG. 9 is a fragmentary sectional view ofmodification 2-3 of the semiconductor device according to the secondembodiment. FIG. 8 is an enlarged plan view of the vicinities of aresistance element 7 of a semiconductor device 1 a. Furthermore, in FIG.8, the position of the resistance element 7 (bonding area 4 a 1) isindicated by a dashed line. FIG. 9 is an enlarged sectional view of thevicinities of the resistance element 7 taken along the dot-dash line X-Xof FIG. 8. In modification 2-3 a change made in the semiconductor device1 a according to the second embodiment will mainly be described.Furthermore, components of the semiconductor device 1 a according tomodification 2-3 which are the same as those included in thesemiconductor device 1 a according to the second embodiment are markedwith the same numerals and descriptions of them will be omitted orsimplified.

With the semiconductor device 1 a according to modification 2-3 aplurality of concave portions 10 a are formed further in the bondingarea 4 a 1 of the circuit pattern 4 a of FIG. 7 over which theresistance element 7 is mounted. That is to say, in modification 2-3 theplurality of concave portions 10 a are formed in the entire surfaceinside an outer peripheral portion of a circuit pattern 4 a.Accordingly, concave portions 10 a under the resistance element 7(bonding area 4 a 1) are filled with a bonding member 7 e. Inmodification 2-3, as with modification 2-1, concave portions 10 a may beformed in the circuit pattern 4 a so as to overlap the outer peripheralportion of the resistance element 7 (bonding area 4 a 1) in plan view.Furthermore, the total volume of the plurality of concave portions 10 aformed in this way is greater than or equal to 0.8 times the volume of ametal block 7 a and smaller than or equal to 1.2 times the volume of themetal block 7 a. The total volume of the plurality of concave portions10 a formed in this way is preferably greater than or equal to 0.9 timesthe volume of the metal block 7 a and smaller than or equal to 1.1 timesthe volume of the metal block 7 a.

In the first embodiment, as stated above, the metal block 7 a(resistance element 7) is mounted over the circuit pattern 4 a. As aresult, a crack may appear in the insulating plate 3 under a cornerportion of the circuit pattern 4 a. In modification 2-3 the total volumeof the concave portions 10 a formed in the circuit pattern 4 a is madeapproximately equal to the volume of the metal block 7 a. As a result, astate which is approximately the same as a state before mounting themetal block 7 a is practically realized. Accordingly, expansion andcontraction of the circuit pattern 4 a are suppressed in temperaturecycling, stress applied to an insulating plate 3 under a corner portionand an outer peripheral portion of the circuit pattern 4 a is relaxed,and the appearance of a crack is suppressed. Furthermore, becauseexpansion and contraction of the entire circuit pattern 4 a are reduced,tin-based solder having small yield stress may be used as the bondingmember 7 e which is solder.

With the semiconductor device 1 a according to modification 2-3, heatgenerated by the resistance element 7 is dissipated and deterioration inthe heat dissipation property of an insulated circuit board 2 issuppressed. Furthermore, stress applied to the insulating plate 3 undera corner portion and the outer peripheral portion of the circuit pattern4 a is relaxed and the appearance of a crack is also suppressed. As aresult, the occurrence of damage to the insulated circuit board 2 isprevented. In addition, the concave portions 10 a are also filled withthe bonding member 7 e and wet-spreading of the bonding member 7 e isprevented. This also improves bonding strength between the resistanceelement 7 and the circuit pattern 4 a. Accordingly, deterioration in thereliability of the semiconductor device 1 a is also suppressed.

(Modification 2-4)

A semiconductor device 1 a according to modification 2-4 will bedescribed by the use of FIG. 10 and FIG. 11. FIG. 10 is a fragmentaryplan view of modification 2-4 of the semiconductor device according tothe second embodiment. FIG. 11 is a fragmentary sectional view ofmodification 2-4 of the semiconductor device according to the secondembodiment. FIG. 10 is an enlarged plan view of the vicinities of aresistance element 7 of a semiconductor device 1 a. FIG. 11 is anenlarged sectional view of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 10. In modification 2-4 achange made in the semiconductor device 1 according to the firstembodiment will mainly be described. Furthermore, components of thesemiconductor device 1 a according to modification 2-4 which are thesame as those included in the semiconductor device 1 according to thefirst embodiment are marked with the same numerals and descriptions ofthem will be omitted or simplified.

With the semiconductor device 1 a according to modification 2-4 aconcave portion having the shape of a groove is formed in the backsurface of the metal block 7 a of the resistance element 7 of thesemiconductor device 1 according to the first embodiment. FIGS. 10 and11 illustrate as a desirable case a case where a concave portion 11 isformed in a continuous loop shape on the outer edge side along the foursides of a metal block 7 a in the back surface of the metal block 7 a.Furthermore, the concave portion 11 is formed just under main currentelectrodes 7 d 1 and 7 d 2 and measurement electrodes 7 d 3 and 7 d 4inside the outer edge of the metal block 7 a. Each corner portion of theconcave portion 11 in the continuous loop shape may have an R-shape inplan view. The width of the concave portion 11 is greater than or equalto 10 percent of the length of each side of the metal block 7 a andsmaller than or equal to 30 percent of the length of each side of themetal block 7 a. The concave portion 11 does not pierce the metal block7 a and the depth of the concave portion 11 is greater than or equal to20 percent of the thickness T1 of the metal block 7 a and smaller thanor equal to 40 percent of the thickness T1 of the metal block 7 a.

With the semiconductor device 1 a according to modification 2-4 theconcave portion 11 is formed in the back surface of the metal block 7 a.By doing so, the volume of the metal block 7 a is reduced. As a result,as with modification 2-3, a state which is approximately equal to astate before mounting the metal block 7 a is realized. Accordingly,expansion and contraction of a circuit pattern 4 a are suppressed intemperature cycling, stress applied to an insulating plate 3 under acorner portion and an outer peripheral portion of the circuit pattern 4a is relaxed, and the appearance of a crack is suppressed. Furthermore,the concave portion 11 is filled with a bonding member 7 e which issolder. This improves bonding strength between the metal block 7 a andthe circuit pattern 4 a.

With the semiconductor device 1 a according to modification 2-4, heatgenerated by the resistance element 7 is dissipated and deterioration inthe heat dissipation property of an insulated circuit board 2 issuppressed. Furthermore, stress applied to the insulating plate 3 undera corner portion and the outer peripheral portion of the circuit pattern4 a is relaxed and the appearance of a crack is also suppressed. As aresult, the occurrence of damage to the insulated circuit board 2 isprevented. In addition, the concave portion 11 is also filled with thebonding member 7 e and wet-spreading of the bonding member 7 e isprevented. This also improves bonding strength between the resistanceelement 7 and the circuit pattern 4 a. Accordingly, deterioration in thereliability of the semiconductor device 1 a is also suppressed.

(Modification 2-5)

A semiconductor device 1 a according to modification 2-5 will bedescribed by the use of FIG. 12 and FIG. 13. FIG. 12 is a fragmentaryplan view of modification 2-5 of the semiconductor device according tothe second embodiment. FIG. 13 is a fragmentary sectional view ofmodification 2-5 of the semiconductor device according to the secondembodiment. FIG. 12 is an enlarged plan view of the vicinities of aresistance element 7 of a semiconductor device 1 a and the resistanceelement 7 outside the dashed line corresponds to a concave portion 11.FIG. 13 is an enlarged sectional view of the vicinities of theresistance element 7 taken along the dot-dash line X-X of FIG. 12. Inmodification 2-5 a change made in the semiconductor device 1 accordingto the first embodiment will mainly be described. Furthermore,components of the semiconductor device 1 a according to modification 2-5which are the same as those included in the semiconductor device 1according to the first embodiment are marked with the same numerals anddescriptions of them will be omitted or simplified.

With the semiconductor device 1 a according to modification 2-5 theconcave portion 11 is formed by making an outer peripheral portion andfour corners of the back surface of a metal block 7 a concave.Accordingly, the concave portion 11 of the metal block 7 a facing acircuit pattern 4 a is filled with a bonding member 7 e and the metalblock 7 a is bonded to the circuit pattern 4 a with the bonding member 7e.

With the semiconductor device 1 a according to modification 2-5 theconcave portion 11 is formed by making the outer peripheral portion andthe four corners of the back surface of the metal block 7 a concave. Asa result, the distance between corner portions of the back surface ofthe metal block 7 a and the circuit pattern 4 a is increased.Accordingly, stress applied to an insulating plate 3 corresponding tothe corner portions of the metal block 7 a is relaxed and the appearanceof a crack is suppressed. Furthermore, the concave portion 11 is filledwith the bonding member 7 e which is solder. This improves bondingstrength between the metal block 7 a and the circuit pattern 4 a.

With the semiconductor device 1 a according to modification 2-5, heatgenerated by the resistance element 7 is dissipated and deterioration inthe heat dissipation property of an insulated circuit board 2 issuppressed. Furthermore, the distance between the corner portions of theback surface of the metal block 7 a and the circuit pattern 4 a isincreased by forming the concave portion 11 obtained by making the outerperipheral portion and the corner portions of the back surface of themetal block 7 a concave. Accordingly, stress applied to the insulatingplate 3 under corner portions and an outer peripheral portion of thecircuit pattern 4 a is relaxed and the appearance of a crack is alsosuppressed. As a result, the occurrence of damage to the insulatedcircuit board 2 is prevented. In addition, the concave portion 11 isalso filled with the bonding member 7 e and wet-spreading of the bondingmember 7 e is prevented. This also improves bonding strength between theresistance element 7 and the circuit pattern 4 a. Accordingly,deterioration in the reliability of the semiconductor device 1 a is alsosuppressed.

Third Embodiment

A semiconductor device according to a third embodiment will be describedby the use of FIG. 14 and FIG. 15. FIG. 14 is a fragmentary plan view ofa semiconductor device according to a third embodiment. FIG. 15 is afragmentary sectional view of the semiconductor device according to thethird embodiment. FIG. 14 is an enlarged plan view of the vicinities ofa resistance element 7 of a semiconductor device 1 b. FIG. 15 is anenlarged sectional view of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 14. In the third embodiment achange made in the semiconductor device 1 according to the firstembodiment will mainly be described. Furthermore, components of thesemiconductor device 1 b which are the same as those included in thesemiconductor device 1 according to the first embodiment are marked withthe same numerals and descriptions of them will be omitted orsimplified.

With the semiconductor device 1 according to the first embodiment theresistance element 7 is arranged over the circuit pattern 4 a. With thesemiconductor device 1 b according to the third embodiment, the backsurface of a circuit pattern 4 a is larger than the front surface of thecircuit pattern 4 a and each side portion is inclined. That is to say, abonding area 4 a 1 to which the resistance element 7 is bonded is set onthe front surface of the circuit pattern 4 a in the third embodiment andthe circuit pattern 4 a in the third embodiment has a trapezoidal shapein side view.

In the case of the first embodiment, as stated above, stress is appliedto the insulating plate 3 under the corner portions of the back surfaceof the circuit pattern 4 a according to expansion and contraction of thecircuit pattern 4 a and a crack tends to appear to the inside of theinsulating plate 3. On the other hand, with the circuit pattern 4 a inthe third embodiment the back surface is situated outside the frontsurface in plan view. As a result, stress applied from each cornerportion of the back surface of the circuit pattern 4 a to the insulatingplate 3 is relaxed and the appearance of a crack is suppressed.Accordingly, as the back surface of the circuit pattern 4 a is madelarger than the front surface of the circuit pattern 4 a, stress appliedto the insulating plate 3 is dispersed and stress applied to a specificarea of the insulating plate 3 is relaxed. However, this depends on thelayout of circuit patterns 4.

As with the second embodiment and each modification of the secondembodiment, a concave portion may be formed in the circuit pattern 4 aor a metal block 7 a of the semiconductor device 1 b according to thethird embodiment. This prevents the occurrence of damage to an insulatedcircuit board 2 more reliably and also improves bonding strength betweenthe resistance element 7 and the circuit pattern 4 a. Accordingly,deterioration in the reliability of the semiconductor device 1 b is alsosuppressed more reliably.

Fourth Embodiment

A semiconductor device according to a fourth embodiment will bedescribed by the use of FIG. 16 and FIG. 17. FIG. 16 is a fragmentaryplan view of a semiconductor device according to a fourth embodiment.FIG. 17 is a fragmentary sectional view of the semiconductor deviceaccording to the fourth embodiment. FIG. 16 is an enlarged plan view ofthe vicinities of a resistance element 7 of a semiconductor device 1 c.FIG. 17 is an enlarged sectional view of the vicinities of theresistance element 7 taken along the dot-dash line X-X of FIG. 16. Inthe fourth embodiment a change made in the semiconductor device 1according to the first embodiment will mainly be described. Furthermore,components of the semiconductor device 1 c which are the same as thoseincluded in the semiconductor device 1 according to the first embodimentare marked with the same numerals and descriptions of them will beomitted or simplified.

With the semiconductor device 1 c according to the fourth embodiment, aconcave portion 12 is formed in the front surface of the circuit pattern4 a of the semiconductor device 1 according to the first embodiment andtherefore an area including the bonding area 4 a 1 to which theresistance element 7 is bonded is concave. A relaxation layer 7 f isformed in the concave portion 12 and the resistance element 7 is bondedto the relaxation layer 7 f. At this time the relaxation layer 7 f issolder. In particular, a material, such as tin-based solder, havingsmall yield stress may be used.

With the semiconductor device 1 c according to the fourth embodiment,the relaxation layer 7 f is formed in the concave portion 12 formed inthe circuit pattern 4 a and the resistance element 7 is arrangedthereover. As a result, the relaxation layer 7 f is thick compared withthe bonding member 7 e in the first embodiment. Accordingly, distortionat the time of expansion and contraction of the circuit pattern 4 a isabsorbed by the relaxation layer 7 f, stress applied to an insulatingplate 3 is relaxed, and the appearance of a crack in the insulatingplate 3 is prevented.

Furthermore, the area of the concave portion 12 formed in the circuitpattern 4 a may be at least the same in plan view as that of the bondingarea 4 a 1 of the circuit pattern 4 a to which the resistance element 7is bonded. Alternatively, the area of the concave portion 12 may belarger in plan view than that of the bonding area 4 a 1 of the circuitpattern 4 a to which the resistance element 7 is bonded. Each cornerportion of the concave portion 12 may have an R-shape in plan view. Inaddition, the concave portion 12 does not pierce the circuit pattern 4a. The depth of the concave portion 12 is set to a degree that thestrength of the circuit pattern 4 a does not lower. The depth of theconcave portion 12 is greater than or equal to 30 percent of thethickness of the circuit pattern 4 a and smaller than or equal to 60percent of the thickness of the circuit pattern 4 a. Moreover, as longas the relaxation layer 7 f has a determined thickness, the back surfaceof a metal block 7 a may enter the circuit pattern 4 a so as to belocated closer to the insulating plate 3 (in the −Z direction) below thefront surface of the circuit pattern 4 a. As a result, the back surfaceof the metal block 7 a and the lower parts of the sides of the metalblock 7 a closer to the back surface thereof are bonded with therelaxation layer 7 f and bonding strength between the metal block 7 aand the circuit pattern 4 a is improved.

Fifth Embodiment

A semiconductor device according to a fifth embodiment will be describedby the use of FIG. 18. FIG. 18 is a fragmentary sectional view of asemiconductor device according to a fifth embodiment. FIG. 3 may bereferred to for a plan view corresponding to FIG. 18. FIG. 18corresponds to a section of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 3. In the fifth embodiment achange made in the semiconductor device 1 according to the firstembodiment will mainly be described. Furthermore, components of asemiconductor device 1 d which are the same as those included in thesemiconductor device 1 according to the first embodiment are marked withthe same numerals and descriptions of them will be omitted orsimplified.

With the semiconductor device 1 d according to the fifth embodiment arelaxation layer 7 f is formed between bonding members 7 e with whichthe resistance element 7 is bonded to the circuit pattern 4 a in thesemiconductor device 1 according to the first embodiment. The relaxationlayer 7 f contains as a main component a material which is smaller inlinear expansion coefficient than a metal block 7 a and a circuitpattern 4 a. Such a material is metal such as molybdenum or Invar.Furthermore, the thickness of the relaxation layer 7 f is greater thanor equal to 10 μm and smaller than or equal to 100 μm.

The back surface of the metal block 7 a may enter the bonding member 7 eon the back surface of the metal block 7 a so as to be located closer toan insulating plate 3 (in the −Z direction) below the front surface ofthe bonding member 7 e. As a result, the back surface of the metal block7 a and the lower parts of the sides of the metal block 7 a are bondedwith the bonding member 7 e and bonding strength between the metal block7 a and the circuit pattern 4 a is improved.

With the semiconductor device 1 d according to the fifth embodiment thecircuit pattern 4 a attempts to expand and contract according to heatgenerated by the resistance element 7. At this time the circuit pattern4 a is put between the relaxation layer 7 f, which is smaller in linearexpansion coefficient than the circuit pattern 4 a, and the insulatingplate 3. This suppresses expansion and contraction of the circuitpattern 4 a. Accordingly, stress applied to the insulating plate 3 isrelaxed and the appearance of a crack in the insulating plate 3 isprevented.

The relaxation layer 7 f put between the bonding members 7 e may beformed in the concave portion 12 of the circuit pattern 4 a in thefourth embodiment. In this case, stress applied to the insulating plate3 is also relaxed and the appearance of a crack in the insulating plate3 is also prevented.

Sixth Embodiment

A semiconductor device according to a sixth embodiment will be describedby the use of FIG. 19 and FIG. 20. FIG. 19 is a fragmentary plan view ofa semiconductor device according to a sixth embodiment. FIG. 20 is afragmentary sectional view of the semiconductor device according to thesixth embodiment. FIG. 19 is an enlarged plan view of the vicinities ofa resistance element 7 of a semiconductor device 1 e. FIG. 20 is anenlarged sectional view of the vicinities of the resistance element 7taken along the dot-dash line X-X of FIG. 19. In the sixth embodiment achange made in the semiconductor device 1 according to the firstembodiment will mainly be described. Furthermore, components of thesemiconductor device 1 e which are the same as those included in thesemiconductor device 1 according to the first embodiment are marked withthe same numerals and descriptions of them will be omitted orsimplified.

With the semiconductor device 1 e according to the sixth embodiment arelaxation layer 8 b is formed between the resistance element 7 and thecircuit pattern 4 a in the semiconductor device 1 according to the firstembodiment. The relaxation layer 8 b is an adhesive containing as a maincomponent silicone or the like. The relaxation layer 8 b is formedbetween the back surface of a metal block 7 a and the front surface of acircuit pattern 4 a and on the lower parts of the sides (on the outerperiphery) of the metal block 7 a. The thickness t1 of the relaxationlayer 8 b formed between the back surface of the metal block 7 a and thefront surface of the circuit pattern 4 a is smaller than or equal to 10μm and is preferably smaller than or equal to 2 μm. Furthermore, thethickness t2 of the relaxation layer 8 b formed on the sides (on theouter periphery) of the metal block 7 a is greater than thickness t1 andis smaller than or equal to 0.8 times the thickness of the metal block 7a. If the relaxation layer 8 b is too thick, then the relaxation layer 8b spreads over a surface (X-Y plane) and may flow down the circuitpattern 4 a.

With the semiconductor device 1 e according to the sixth embodiment thecircuit pattern 4 a attempts to expand and contract according to heatgenerated by the resistance element 7. At this time distortion caused bydeformation of the circuit pattern 4 a which expands and contracts isabsorbed by the relaxation layer 8 b. Accordingly, stress applied to aninsulating plate 3 is relaxed and the appearance of a crack in theinsulating plate 3 is prevented.

The relaxation layer 8 b may be formed in the concave portion 12 of thecircuit pattern 4 a in the fourth embodiment. In this case, stressapplied to the insulating plate 3 is also relaxed and the appearance ofa crack in the insulating plate 3 is also prevented.

According to the disclosed techniques, deterioration in the heatdissipation property of an insulated circuit board over which aresistance element is arranged is suppressed and a semiconductor devicefor which deterioration in reliability is suppressed is provided.

All examples and conditional language provided herein are intended forthe pedagogical purposes of aiding the reader in understanding theinvention and the concepts contributed by the inventor to further theart, and are not to be construed as limitations to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although one or more embodiments of thepresent invention have been described in detail, it should be understoodthat various changes, substitutions, and alterations could be madehereto without departing from the spirit and scope of the invention.

What is claimed is:
 1. A semiconductor device, comprising: a resistanceelement including a metal block, a resin layer disposed on the metalblock, and a resistance film disposed on the resin layer; and aninsulated circuit board including an insulating plate, and a circuitpattern having a front surface, the circuit pattern being disposed onthe insulating plate and having a bonding area on the front surface ofthe circuit pattern to which a back surface of the metal block of theresistance element is bonded, an area of the circuit pattern beinglarger in a plan view of the semiconductor device than an area of theresistance element, wherein the metal block has a thickness greater thana thickness of the circuit pattern in a direction orthogonal to the backsurface of the metal block.
 2. The semiconductor device according toclaim 1, wherein one or more first concavities are formed at the frontsurface of the circuit pattern.
 3. The semiconductor device according toclaim 2, wherein the bonding area has a rectangular shape with fourcorners in the plan view, and the one or more first concavities includesa plurality of first concavities that are respectively disposed incorner areas corresponding to the four corners of the bonding area. 4.The semiconductor device according to claim 3, wherein a plurality ofsecond concavities is disposed along an outer periphery of the frontsurface of the circuit pattern, between two of the corner areas that areadjacent to each other.
 5. The semiconductor device according to claim4, wherein a plurality of third concavities is formed in an area insidethe outer periphery of the front surface of the circuit pattern.
 6. Thesemiconductor device according to claim 5, wherein a total volume of thefirst, second, and third concavities is in a range of 0.8 times to 1.2times a volume of the metal block.
 7. The semiconductor device accordingto claim 5, wherein: the resistance element is bonded to the bondingarea with a bonding material; and the first, second, and thirdconcavities formed in the bonding area are also filled with the bondingmaterial.
 8. The semiconductor device according to claim 3, wherein atleast one of the one or more first concavities overlap an outerperiphery of the bonding area in the plan view.
 9. The semiconductordevice according to claim 2, wherein: the resistance element includesmain current electrodes provided at each of opposite sides of theresistance film disposed on the resin layer; and at least one of the oneor more first concavities is respectively provided along the maincurrent electrodes in the back surface of the metal block under each ofthe main current electrodes.
 10. The semiconductor device according toclaim 9, wherein the one or more first concavities form a continuousloop shape along an outer periphery of the back surface of the metalblock, the outer periphery including an area under the main currentelectrodes of the back surface of the metal block.
 11. The semiconductordevice according to claim 1, wherein: a size of a back surface of thecircuit pattern is larger than a size of a front surface of the circuitpattern in the plan view so that each side surface of the circuitpattern is inclined in a side view of the semiconductor device.
 12. Thesemiconductor device according to claim 1, wherein the resistanceelement is bonded to the bonding area of the circuit pattern with arelaxation layer.
 13. The semiconductor device according to claim 12,wherein: the circuit pattern has a concave area including the bondingarea and is recessed from the front surface of the circuit patterntoward the insulating plate; and the relaxation layer is disposed in theconcave area.
 14. The semiconductor device according to claim 12,wherein the relaxation layer is solder.
 15. The semiconductor deviceaccording to claim 12, wherein the relaxation layer contains as a maincomponent a metal having a linear expansion coefficient smaller thanlinear expansion coefficients of the circuit pattern and the metalblock.
 16. The semiconductor device according to claim 15, wherein themetal is molybdenum or Invar.
 17. The semiconductor device according toclaim 12, wherein the relaxation layer is an adhesive.
 18. Thesemiconductor device according to claim 12, wherein the relaxation layeris disposed between the resistance element and the bonding area of thecircuit pattern, and along an outer periphery of the resistance elementadjacent to the circuit pattern.